In many electronics applications, analog signals must be digitally encoded or decoded at any one of a number of sample rates depending on a selected mode of operation. In the field of digital signal processing (DSP), analog conversion is required to receive/transmit analog signals to/from a digital environment. The sample rate or sample frequency (F.sub.s) used for the conversion for each application will be dependent upon the nature of the analog data. For example, DSP applications that require analog conversion at different sample rates include receiving and transmitting modem data, playing compact disk audio (F.sub.s =44.1 kHz), transmitting and receiving voice data (F.sub.s =8 kHz).
When designing a system or semiconductor device to implement multi-functional DSP, it is very limiting to only allow the system to implement functions having sample rates that are divisible from a practical crystal frequency. Thus, it is necessary to generate a clock asynchronous to the crystal to perform the sampling. In the prior art, a phase locked loop (PLL) generates the required clock for the digital-to-analog (D/A) or analog to-digital (A/D) conversions.
As seen in FIG. 1, there is shown a digital signal processing system of the prior art using a PLL to generate the sample clock used to produce the digital-to-analog conversion. System 100 includes a digital signal processor (DSP) 110 that performs a specified function on the received digital data (DATA), and outputs modified data (DATA Fs (SAMPLE)) to a D/A converter 120 to generate the required analog output. For example, system 100 could be a computer modem for converting digital data and outputting the equivalent analog data on a telephone line. In order to produce the appropriate input clock for the D/A converter 120, PLL 130 locks to a clock (CLK.sub.Fs) operating at the frequency (F.sub.s) of DATA. PLL 130 locks to CLK.sub.Fs and generates an output clock CLK.sub.FsX having a frequency equal to F.sub.s times X, wherein X is a selected number that provides the appropriate sampling clock for the D/A converter 120. In this way, the PLL is used to produce the necessary asynchronous clock, relative to the system clock (CLK.sub.Q), to properly convert the DSP 110 output data into analog data.
The use of a PLL to produce the asynchronous clock for analog conversion has significant commercial disadvantages. For example, it is difficult to make a low noise PLL device, that does not affect conversion performance. Also, verification of the device performance is complicated because long simulation times are required to simulate the mixed-mode operation of a PLL, and further a PLL circuit is much more process sensitive than standard digital circuits.
Another prior art solution to this problem of sample rate conversion is to perform additional processing within the DSP to perform the digital sample rate conversion. This conversion allows the converter to be clocked at a frequency derived from the system clock frequency. This solution eliminates the need for a PLL. However, this solution is difficult and costly to implement in terms of the increased number of instructions required and it also has higher power consumption from the increased use of the multiplier to obtain a high quality result.
As can be seen, there is a need for an accurate, simple and robust solution to asynchronous sample rate conversion that does not have the design disadvantages of the phase lock loop solution and the high signal processing requirements of the DSP solution.